Heuristic Tradeoffs between Prefetching and Spilling Windows to Reduce Memory Spills in Vliw Asips

One of the challenging tasks in code generation for embedded systems is register allocation and assignment, wherein, one decides on the placement and lifetimes of variables in registers. When there are more live variables than registers, some variables need to be spilled to memory and restored later. In this paper we propose a policy that minimizes the number of spills – which is critical for portable embedded systems since it leads to decreased energy consumption. We argue however, that schedules with a minimal number of spills do not necessarily have minimum latency. Accordingly, we propose a class of policies that explore tradeoffs between assignments leading to schedules with low latency versus those leading to low energy consumption. Our experimental results demonstrate the effectiveness of the proposed policies.